CN105187051A - Power and area optimization method of incomplete certain Reed-Muller circuit based on NSGA-II - Google Patents
Power and area optimization method of incomplete certain Reed-Muller circuit based on NSGA-II Download PDFInfo
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Abstract
The invention provides a power and area optimization method of an incomplete certain Reed-Muller circuit based on NSGA-II. The method comprises the steps of (1) converting an incomplete certain Boolean logic function into a zero polarity incomplete certain RM expression, (2) encoding the binary number of don't care term option of the incomplete certain Boolean logic function as a chromosome, (3) establishing a power area estimation model, (4) establishing a power area target function, (5) establishing fitness functions related to a power and an area, (6) determining a constraint, (7) initializing parameters, (8) generating an initial population and performing non-dominated sorting, (9) performing selection crossover and mutation and generating a son generation population, (10) combining father and son generation populations and performing non-dominated sorting, (11) calculating an individual crowding degree in a non-dominated layer and forming new father and son generation populations, (12) performing selection crossover and mutation on the new father and son generation populations and generating a new son generation population, (13) returning to the step (10) if current evolution generation number is smaller than or equal to a maximum evolution generation number, otherwise, outputting an optimal solution set, and (14) selecting an optimal don't care term option from the optimal solution set and obtaining a corresponding complete certain RM expression.
Description
Technical field
The present invention relates to and not exclusively determine Reed-Muller circuit power consumption and area-optimized method, particularly relating to one based on NSGA-II for not exclusively determining Reed-Muller circuit power consumption and area-optimized method.Belong to logical function and logical circuit technical field.
Background technology
Logical function both can by the Boolean logic realization based on AND/OR/NOT computing, also can by Reed-Muller (RM) logic realization based on AND/XOR or XNOR/OR computing.For the XOR comparatively frequently partial circuit such as arithmetical circuit, parity checker and telecommunication circuit, compared with Boolean logic realization form, RM logic realization form has larger advantage in power consumption, Area and Speed etc.Again due to the change that the change of a certain input of XOR gate can directly cause it to export, so RM logical circuit also has good testability.Therefore, RM logical circuit has caused the extensive concern of people, and the optimization method developed based on RM logical circuit is to the important supplement of method for optimizing integrated circuit and perfect.
More and more higher along with integrated circuit integrated level, power consumption also increases thereupon.The power consumption of quick increase has become a large bottleneck of restriction integrated circuit development.Industrial quarters pursues high density and high-performance from simple to the design constraint of integrated circuit, then enters the impact considering the aspect such as power consumption and area.Particularly in a portable device, power consumption and the area-constrained primary constraint having become chip design.Therefore, the power consumption of integrated circuit and the area-optimized importance having become circuit optimization.
Logical function is represented by the Boolean expression of minterm sum form usually.Outlier is a kind of special minterm in Boolean expression, and whether this occurs the function that all can not affect logical circuit in Boolean expression, but can affect the performance of logical circuit.The logical function comprising outlier is called not exclusively determines logical function, and the RM logical circuit corresponding to it is called not exclusively determines RM circuit.One is comprised to the Boolean function of m outlier, available one group of binary number w being called " outlier choice "
1w
2w
iw
mcharacterize its corresponding outlier and whether write logical function.If w
ibe 0, represent that the outlier of its correspondence does not write logical function; If w
ibe 1, then represent the outlier write logical function of its correspondence.After determining that outlier is accepted or rejected, not exclusively determine that logical function becomes and determine logical function completely, not exclusively determine that RM circuit becomes and determine RM circuit completely.Can draw, different outlier is accepted or rejected, and the circuit performances such as the RM circuit structure of its correspondence, power consumption and area are not quite similar.Research shows, Appropriate application outlier can simplify the expression formula of logical function, and then can the power consumption of optimized circuit and area.
But the existing optimization method for the RM logical circuit overwhelming majority does not all consider the impact of outlier, relatively deficient to the research of optimization method of the RM logical circuit comprising outlier.In addition, research for the RM logical circuit optimization considering outlier mainly concentrates on and comprises outlier RM expression formula dipole inversion, and utilize outlier to carry out the abbreviation of logical expression, seldom there is research and utilization outlier to carry out power consumption to RM logical circuit and area is optimized simultaneously.In addition, the research simultaneously optimized for RM logical circuit power consumption and area at present, nearly all use traditional weighted sum method that power consumption and area-optimized this multi-objective optimization question are converted into single-object problem to solve, coefficient is determined by optimal design personnel, in order to obtain approximate Pareto optimal solution set, need to use different coefficients to implement dynamic optimization.But conventional weight summation approach, when solving multi-objective optimization question, exists and cannot solve the shortcomings such as the distribution of non-convex Pareto forward position and solution is even not.Further, need manually to arrange the weights that many groups are different, computing repeatedly just can obtain Pareto optimal solution set, because each optimizing process is separate, causes the result that obtains very inconsistent, makes optimal design personnel be difficult to make effective decision-making.Therefore, for RM logical circuit power consumption and area-optimized this multi-objective optimization question, need to find the more effective intelligent algorithm of one to obtain Pareto optimal solution set.
Traditional Multipurpose Optimal Method when solving multi-objective optimization question, exist responsive to the optimum front end of Pareto, the heuristic knowledge needed for Solve problems cannot be obtained and must run and repeatedly could obtain the shortcomings such as Pareto optimal solution set.Therefore, in recent years the research of Multipurpose Optimal Method is mainly concentrated on and have on the evolution algorithm of intrinsic advantage, wherein adopt the non-dominated sorted genetic algorithm NSGA-II of elitism strategy to demonstrate larger advantage in numerous evolution algorithm.At present, although about the theoretical research of NSGA-II and application study all more deep, seldom have up to now research by NSGA-II algorithm application RM logical circuit power consumption and area-optimized on.
In sum, there are following problems in the existing optimizing research for RM logical circuit:
(1) when optimizing RM logic circuit synthesis, the impact of outlier on circuit performance is not considered.In fact, consider that outlier can make the effect of optimization of RM logical circuit better.
(2) for considering that the research of RM logical circuit optimization of outlier mainly concentrates on the abbreviation comprising outlier RM expression formula dipole inversion and logical function expression formula, research and utilization outlier is seldom had to carry out power consumption to RM logical circuit and area is optimized simultaneously.
(3) optimization of RM logical circuit is a multi-objective optimization question in essence, needs to consider multiple performance objective.But major part only belongs to single object optimization for the research of RM logical circuit optimization, namely only power consumption is optimized, or only area is optimized, power consumption is not carried out to RM logical circuit and area is optimized simultaneously.
(4) research simultaneously optimized of the existing power consumption for RM logical circuit and area, nearly all uses conventional weight summation approach that power consumption and area-optimized this multi-objective optimization question are converted into single-object problem and solves.But, due to conventional weight summation approach exist cannot solve non-convex Pareto forward position, solution distribution not evenly, need manually to arrange the different weights of many groups and computing repeatedly just can obtain the many disadvantages such as Pareto optimal solution set, thus cause the less effective of RM logical circuit power consumption based on weighted sum method and area-optimized method, there is certain limitation in actual applications.
Summary of the invention
For solving the problem, the invention provides a kind of based on NSGA-II for not exclusively determining the power consumption of Reed-Muller circuit and area-optimized method.First the boolean logic function comprising outlier is converted to the RM expression formula not exclusively determined of zero polarity by the present invention, then the one group of best outlier utilizing NSGA-II algorithm search simultaneously to have better power consumption and area performance is accepted or rejected, the best outlier finally obtained according to search is accepted or rejected, and obtains the completely specified RM expression formula simultaneously with better power consumption and area performance.The present invention utilizes NSGA-II algorithm to accept or reject to search for best outlier, can obtain one group of best outlier simultaneously with better power consumption and area performance fast and effectively and accept or reject, can meet the demand not exclusively determining RM logical circuit actual optimization well.
Specifically, the present invention is a kind of to be used for not exclusively determining Reed-Muller circuit power consumption and area-optimized method based on NSGA-II, and the method concrete steps comprise:
Step 1, what utilize list technique the boolean logic function (not exclusively determining boolean logic function) comprising outlier to be converted to zero polarity not exclusively determines RM expression formula;
Step 2, will not exclusively determine that the binary number that the outlier of boolean logic function is accepted or rejected is encoded to chromosome;
Step 3, according to the feature of RM logical circuit, sets up power consumption model and Area Model;
Step 4, according to power consumption model and the Area Model of RM logical circuit, sets up power dissipation objectives function and area target function respectively;
Step 5, according to power dissipation objectives function and area target function, sets up the fitness function relevant to power consumption and the fitness function relevant with area respectively;
Step 6, according to RM logical circuit power consumption and area-optimized needs, determines constraints;
Step 7, carries out initialization operation to parameter, and the current evolutionary generation of initialization is 1;
Step 8, produces initial population at random, and performs non-dominated ranking to it;
Step 9, performs selection, crossover and mutation operation, obtains progeny population, and adds 1 operation to current evolutionary generation execution;
Step 10, merges parent population and progeny population, and performs quick non-dominated ranking;
Step 11, carries out crowding calculating to the individuality in each non-dominant layer, and selects according to the crowding of non-dominant relation and individuality the parent population that some individual compositions are new;
Step 12, performs selection, crossover and mutation operation to parent population new described in step 11, generates new progeny population, and adds 1 operation to current evolutionary generation execution;
Step 13, if current evolutionary generation is less than or equal to maximum evolutionary generation, then returns step 10; Otherwise export Pareto optimal solution set, one group of best outlier namely simultaneously with better power consumption and area performance is accepted or rejected;
Step 14, according to actual optimization demand, selects one or more outlier to accept or reject from Pareto optimal solution set, obtain with it corresponding there is better power consumption and area performance determine RM expression formula completely.
Wherein, step 1 comprises:
Step 1.1, by n input variable and the boolean logical expression comprising m outlier is expressed as the form of list, list hurdle is input variable x
n, x
n-1... x
i..., x
2, x
1, 1≤i≤n and flag bit f;
Step 1.2, is set to 1 by the flag bit f of each minterm, and the flag bit f of m outlier is set to w respectively
1, w
2..., w
m, W
i∈ { 0,1}, 1≤i≤m.List behavior < L
nl
n-1... L
i... L
2l
1, f >, 1≤i≤n, L
i∈ { 0,1}, f ∈ { 1, w
1, w
2..., w
m;
Step 1.3, by n assignment to j;
Step 1.4, if list row has < L
n... L
j+10L
j-1... L
1, f >, then produce newline < L
n... L
j+11L
j-1... L
1, f >;
Step 1.5, except flag bit, if remainder is identical with the remainder of certain a line in list in the new row produced, then xor operation is carried out to the new flag bit produced in the flag bit in going and list in this line, and by the result assignment of xor operation to the flag bit in this line in list, and delete the new row produced; Otherwise, the row newly produced is added to the afterbody of former list row;
Step 1.6, performs step 1.5 to the row of all new generations, and subtracts 1 operation to j execution;
Step 1.7, if j is greater than 1, then returns step 1.4; Otherwise what export zero polarity not exclusively determines RM expression formula.
Wherein, calculate chromosomal fitness value to comprise:
1, solve zero corresponding with it polarity according to chromosome and determine RM expression formula completely;
2, determine RM expression formula completely according to fitness function and zero polarity, calculate fitness value.
Wherein, solve zero polarity corresponding to chromosome and determine that RM expression formula comprises completely:
1, the flag bit determining each outlier is accepted or rejected according to outlier;
2, according to the flag bit of each outlier, calculate the flag bit that zero polarity not exclusively determines all list row in the list that RM expression formula is corresponding;
3, if the flag bit in list row is 0, then delete this row; If the flag bit in list row is 1, then retain this list row;
4, above-mentioned steps 3 is performed to list row all in list;
5, show that zero polarity determines RM expression formula completely according to the list row retained in last list.
Beneficial functional of the present invention is:
(1) from the reality of RM logical circuit optimization, simultaneously using power consumption and area as optimization aim, with only consider single performance as optimization aim method compared with, more can meet the demand of actual optimization;
(2) RM logical circuit is carried out to power consumption and area-optimized time, consider the impact of outlier on circuit performance, compared with not considering the optimization method of outlier, the effect of optimization of power consumption and area is better;
(3) utilize in multi-objective Evolutionary Algorithm the NSGA-II with greater advantage to not exclusively determining that RM logical circuit carries out power consumption and area is optimized simultaneously, one group of best outlier can simultaneously fast and effectively with better power consumption and area performance is accepted or rejected.Optimal design personnel can according to actual optimization demand, select one or more best outlier to accept or reject, so obtain there is better power consumption and area performance simultaneously determine RM expression formula completely.
Accompanying drawing explanation
Fig. 1 be of the present invention based on NSGA-II for not exclusively determining the flow chart of Reed-Muller circuit power consumption and area-optimized method.
Fig. 2 be of the present invention based on NSGA-II for not exclusively determining the enforcement illustration of Reed-Muller circuit power consumption and area-optimized method.
Embodiment
Describe the present invention below in conjunction with the drawings and specific embodiments, but not as a limitation of the invention.
Fig. 1 be of the present invention based on NSGA-II for not exclusively determining the flow chart of Reed-Muller circuit power consumption and area-optimized method.As shown in Figure 1, the method comprises:
Step 1, utilizes list technique not exclusively to determine RM expression formula by what not exclusively determine that boolean logic function is converted to zero polarity;
Step 2, will not exclusively determine that the binary number that the outlier of boolean logic function is accepted or rejected is encoded to chromosome;
Step 3, according to the feature of RM logical circuit, sets up power estim ation model and Class area estimation model respectively;
Step 4, according to the power estim ation model determined and Class area estimation model, sets up power dissipation objectives function and the area target function of RM logical circuit respectively;
Step 5, according to power dissipation objectives function and area target function, sets up the fitness function relevant to power consumption and the fitness function relevant with area respectively;
Step 6, according to RM logical circuit power consumption and area-saving design requirement, determines constraints;
Step 7, initialization operation is carried out to parameter, namely binary coding variable number, fitness function number, constraints number, crossover probability, mutation probability, population scale, maximum evolutionary generation and random seed etc. are set, and the current evolutionary generation of initialization is 1;
Step 8, produces initial population at random, and performs non-dominated ranking to it;
Step 9, performs selection, crossover and mutation operation, produces progeny population, and adds 1 operation to current evolutionary generation execution;
Step 10, merges parent population and progeny population, and performs quick non-dominated ranking;
Step 11, calculates the crowding of each individuality in non-dominant layer, and selects according to the crowding of non-dominant relation and individuality the parent population that individual composition is new;
Step 12, performs selection, crossover and mutation operation to parent population new described in step 11, generates new progeny population, and adds 1 operation to current evolutionary generation execution;
Step 13, if current evolutionary generation is less than or equal to maximum evolutionary generation, then returns step 10; Otherwise export Pareto optimal solution set, one group of best outlier namely simultaneously with better power consumption and area performance is accepted or rejected;
Step 14, according to actual optimization demand, selects one or more best outlier to accept or reject from Pareto optimal solution set, obtain with it corresponding there is better power consumption and area performance determine RM expression formula completely.
Wherein, step 1 comprises:
Step 1.1, by n input variable and the boolean logical expression comprising m outlier is expressed as the form of list, list hurdle is input variable x
n, x
n-1... x
i..., x
2, x
1, 1≤i≤n and flag bit f;
Step 1.2, is set to 1 by the flag bit f of each minterm, and the flag bit f of m outlier is set to w respectively
1, w
2..., w
m, W
i∈ { 0,1}, 1≤i≤m.List behavior < L
nl
n-1... L
i... L
2l
1, f >, 1≤i≤n, L
i∈ { 0,1}, f ∈ { 1, w
1, w
2..., w
m;
Step 1.3, by n assignment to j;
Step 1.4, if list row has < L
n... L
j+10L
j-1... L
1, f >, then produce newline < L
n... L
j+11L
j-1... L
1, f >;
Step 1.5, except flag bit, if remainder is identical with the remainder of certain a line in list in the new row produced, then xor operation is carried out to the new flag bit produced in the flag bit in going and list in this line, and by the result assignment of xor operation to the flag bit in this line in list, and delete the new row produced; Otherwise, the row newly produced is added to the afterbody of former list row;
Step 1.6, performs step 1.5 to the row of all new generations, and subtracts 1 operation to j execution;
Step 1.7, if j is greater than 1, then returns step 1.4; Otherwise what export zero polarity not exclusively determines RM expression formula.
Wherein, calculate chromosomal fitness value to comprise:
1, solve zero corresponding with it polarity according to chromosome and determine RM expression formula completely;
2, determine RM expression formula completely according to fitness function and zero polarity, calculate fitness value.
Wherein, solve zero polarity corresponding to chromosome and determine that RM expression formula comprises completely:
1, the flag bit determining each outlier is accepted or rejected according to outlier;
2, according to the flag bit of each outlier, calculate the flag bit that zero polarity not exclusively determines all list row in the list that RM expression formula is corresponding;
3, if the flag bit in list row is 0, then delete this row; If the flag bit in list row is 1, then retain this list row;
4, above-mentioned steps 3 is performed to list row all in list;
5, show that zero polarity determines RM expression formula completely according to the list row retained in last list.
Fig. 2 be one embodiment of the invention based on NSGA-II for not exclusively determining Reed-Muller circuit power consumption and area-optimized method schematic diagram, for 6 input variables there is the boolean logic function of 4 outliers, composition graphs 2 enumerate of the present invention based on NSGA-II for not exclusively determining Reed-Muller circuit power consumption and area-optimized method one embodiment.This embodiment based on NSGA-II be used for not exclusively determine that Reed-Muller circuit power consumption and area-optimized method comprise:
Step 1, utilize list technique by 6 input variables and the boolean logic function with 4 outliers be converted to zero polarity not exclusively determine RM expression formula;
Step 2, not exclusively determines that by this binary number that outlier of logical function is accepted or rejected is encoded to chromosome;
Step 3, adopts and considers that the power estim ation model of temporal correlation is as power consumption model; Multi input AND/XOR door in RM logical circuit is decomposed into two input AND/XOR doors, and using the quantity sum of XOR gate and AND door in two input AND/XOR doors as Class area estimation model;
Step 4, respectively according to the power estim ation model determined and Class area estimation model, sets up power dissipation objectives function and the area target function of RM logical circuit;
Step 5, respectively according to power dissipation objectives function and area target function, sets up the fitness function relevant to power consumption and the fitness function relevant with area;
Step 6, in this case for simplicity, does not arrange constraints;
Step 7, initialization is carried out to parameter, arrange that binary coding variable number is 4, fitness function number is 2, constraints number is 0, crossover probability is 0.8, mutation probability is 0.05, population scale is 100, maximum evolutionary generation is 100, random seed is 0.5, and the current evolutionary generation of initialization is 1;
Step 8, produces initial population at random, and performs non-dominated ranking to it;
Step 9, performs selection, crossover and mutation operation, produces progeny population, and adds 1 operation to current evolutionary generation execution; Wherein, select operation to adopt binary algorithm of tournament selection, interlace operation adopts simulation binary system to intersect, and mutation operation adopts binary system variation;
Step 10, merges parent population and progeny population, and carries out quick non-dominated ranking;
Step 11, calculates the crowding of each individuality in non-dominant layer, and selects suitable individuality to form new parent population according to the crowding of non-dominant relation and individuality;
Step 12, performs selection, crossover and mutation operation to parent population new described in step 11, generates new progeny population, and adds 1 operation to current evolutionary generation execution; Wherein, select operation to adopt binary algorithm of tournament selection, interlace operation adopts simulation binary system to intersect, and mutation operation adopts binary system variation;
Step 13, if current evolutionary generation is less than or equal to maximum evolutionary generation, then returns step 10; Otherwise export Pareto optimal solution set, one group of best outlier namely simultaneously with better power consumption and area performance is accepted or rejected;
Step 14, selects 0010 to accept or reject as best outlier from Pareto optimal solution set, and accepts or rejects 0010 according to this best outlier and solve and correspondingly with it determine RM expression formula completely.
Certainly; the present invention also can have other various embodiments; when not deviating from the present invention's spirit and essence thereof; those of ordinary skill in the art are when making various corresponding change and distortion according to the present invention, but these change accordingly and are out of shape the protection range that all should belong to the claim appended by the present invention.
Claims (4)
1. be used for not exclusively determining Reed-Muller circuit power consumption and an area-optimized method based on NSGA-II, it is characterized in that: it comprises following steps:
Step 1, what utilize list technique the boolean logic function comprising outlier to be converted to zero polarity not exclusively determines RM expression formula;
Step 2, will not exclusively determine that the binary number that the outlier of boolean logic function is accepted or rejected is encoded to chromosome;
Step 3, according to the feature of RM logical circuit, sets up power consumption model and Area Model;
Step 4, according to power consumption model and the Area Model of RM logical circuit, sets up power dissipation objectives function and area target function respectively;
Step 5, according to power dissipation objectives function and area target function, sets up the fitness function relevant to power consumption and the fitness function relevant with area respectively;
Step 6, according to RM logical circuit power consumption and area-optimized needs, determines constraints;
Step 7, carries out initialization operation to parameter, and the current evolutionary generation of initialization is 1;
Step 8, produces initial population at random, and performs non-dominated ranking to it;
Step 9, performs selection, crossover and mutation operation, obtains progeny population, and adds 1 operation to current evolutionary generation execution;
Step 10, merges parent population and progeny population, and performs quick non-dominated ranking;
Step 11, carries out crowding calculating to the individuality in each non-dominant layer, and selects according to the crowding of non-dominant relation and individuality the parent population that some individual compositions are new;
Step 12, performs selection, crossover and mutation operation to parent population new described in step 11, generates new progeny population, and adds 1 operation to current evolutionary generation execution;
Step 13, if current evolutionary generation is less than or equal to maximum evolutionary generation, then returns step 10; Otherwise export Pareto optimal solution set, one group of best outlier namely simultaneously with better power consumption and area performance is accepted or rejected;
Step 14, according to actual optimization demand, selects one or more outlier to accept or reject from Pareto optimal solution set, obtain with it corresponding there is better power consumption and area performance determine RM expression formula completely.
2. one according to claim 1 is used for not exclusively determining Reed-Muller circuit power consumption and area-optimized method based on NSGA-II, it is characterized in that: described step 1 comprises following concrete steps:
Step 1.1, by n input variable and the boolean logical expression comprising m outlier is expressed as the form of list, list hurdle is input variable x
n, x
n-1... x
i..., x
2, x
1, 1≤i≤n and flag bit f;
Step 1.2, is set to 1 by the flag bit f of each minterm, and the flag bit f of m outlier is set to w respectively
1, w
2..., w
m, W
i∈ { 0,1}, 1≤i≤m; List behavior
1≤i≤n, L
i∈ { 0,1}, f ∈ { 1, w
1, w
2..., w
m;
Step 1.3, by n assignment to j;
Step 1.4, if list row has < L
n... L
j+10L
j-1... L
1, f >, then produce newline < L
n... L
j+11L
j-1... L
1, f >;
Step 1.5, except flag bit, if remainder is identical with the remainder of certain a line in list in the new row produced, then xor operation is carried out to the new flag bit produced in the flag bit in going and list in this line, and by the result assignment of xor operation to the flag bit in this line in list, and delete the new row produced; Otherwise, the row newly produced is added to the afterbody of former list row;
Step 1.6, performs step 1.5 to the row of all new generations, and subtracts 1 operation to j execution;
Step 1.7, if j is greater than 1, then returns step 1.4; Otherwise what export zero polarity not exclusively determines RM expression formula.
3. one according to claim 1 is used for not exclusively determining Reed-Muller circuit power consumption and area-optimized method based on NSGA-II, it is characterized in that: calculate chromosomal fitness value and comprise:
Step 1, solves zero corresponding with it polarity according to chromosome and determines RM expression formula completely;
Step 2, determines RM expression formula completely according to fitness function and zero polarity, calculates fitness value.
4. one according to claim 1 is used for not exclusively determining Reed-Muller circuit power consumption and area-optimized method based on NSGA-II, it is characterized in that: solve zero polarity corresponding to chromosome and determine that RM expression formula comprises completely:
Step 1, accepts or rejects the flag bit determining each outlier according to outlier;
Step 2, according to the flag bit of each outlier, calculates the flag bit that zero polarity not exclusively determines all list row in the list that RM expression formula is corresponding;
Step 3, if the flag bit in list row is 0, then deletes this row; If the flag bit in list row is 1, then retain this list row;
Step 4, performs above-mentioned steps 3 to list row all in list;
According to the list row retained in last list, step 5, show that zero polarity determines RM expression formula completely.
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