DE69837791D1 - VERFAHREN UND GERÄT FÜR EFFIZIENTE, SYNCHRONE MIMD-OPERATIONEN MIT iVLIW PE-ZU-PE KOMMUNIKATIONEN - Google Patents

VERFAHREN UND GERÄT FÜR EFFIZIENTE, SYNCHRONE MIMD-OPERATIONEN MIT iVLIW PE-ZU-PE KOMMUNIKATIONEN

Info

Publication number
DE69837791D1
DE69837791D1 DE69837791T DE69837791T DE69837791D1 DE 69837791 D1 DE69837791 D1 DE 69837791D1 DE 69837791 T DE69837791 T DE 69837791T DE 69837791 T DE69837791 T DE 69837791T DE 69837791 D1 DE69837791 D1 DE 69837791D1
Authority
DE
Germany
Prior art keywords
simd
mimd
control
employed
ivliw
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69837791T
Other languages
English (en)
Other versions
DE69837791T2 (de
Inventor
Gerald G Pechanek
Thomas L Drabenstott
Juan Guillermo Revilla
David Carl Strube
Grayson Morris
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Altera Corp
Original Assignee
Altera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Altera Corp filed Critical Altera Corp
Publication of DE69837791D1 publication Critical patent/DE69837791D1/de
Application granted granted Critical
Publication of DE69837791T2 publication Critical patent/DE69837791T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145Instruction analysis, e.g. decoding, instruction word fields
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145Instruction analysis, e.g. decoding, instruction word fields
    • G06F9/3016Decoding the operand specifier, e.g. specifier format
    • G06F9/30167Decoding the operand specifier, e.g. specifier format of immediate specifier, e.g. constants
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3802Instruction prefetching
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3853Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution of compound instructions
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3885Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3885Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units
    • G06F9/3887Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units controlled by a single instruction for multiple data lanes [SIMD]
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3885Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units
    • G06F9/3889Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units controlled by multiple instructions, e.g. MIMD, decoupled access or execute
DE69837791T 1997-11-07 1998-11-06 VERFAHREN UND GERÄT FÜR EFFIZIENTE, SYNCHRONE MIMD-OPERATIONEN MIT iVLIW PE-ZU-PE KOMMUNIKATIONEN Expired - Lifetime DE69837791T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US6461997P 1997-11-07 1997-11-07
US64619P 1997-11-07
PCT/US1998/023650 WO1999024903A1 (en) 1997-11-07 1998-11-06 METHODS AND APPARATUS FOR EFFICIENT SYNCHRONOUS MIMD OPERATIONS WITH iVLIW PE-to-PE COMMUNICATION

Publications (2)

Publication Number Publication Date
DE69837791D1 true DE69837791D1 (de) 2007-06-28
DE69837791T2 DE69837791T2 (de) 2007-10-18

Family

ID=22057176

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69837791T Expired - Lifetime DE69837791T2 (de) 1997-11-07 1998-11-06 VERFAHREN UND GERÄT FÜR EFFIZIENTE, SYNCHRONE MIMD-OPERATIONEN MIT iVLIW PE-ZU-PE KOMMUNIKATIONEN

Country Status (10)

Country Link
US (3) US6151668A (de)
EP (1) EP1029266B1 (de)
JP (1) JP4156794B2 (de)
KR (1) KR20010031884A (de)
CN (1) CN100380313C (de)
AT (1) ATE362623T1 (de)
CA (1) CA2310584A1 (de)
DE (1) DE69837791T2 (de)
IL (1) IL135953A0 (de)
WO (1) WO1999024903A1 (de)

Families Citing this family (74)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6798834B1 (en) 1996-08-15 2004-09-28 Mitsubishi Denki Kabushiki Kaisha Image coding apparatus with segment classification and segmentation-type motion prediction circuit
US6366999B1 (en) * 1998-01-28 2002-04-02 Bops, Inc. Methods and apparatus to support conditional execution in a VLIW-based array processor with subword execution
US6219776B1 (en) * 1998-03-10 2001-04-17 Billions Of Operations Per Second Merged array controller and processing element
US6356994B1 (en) * 1998-07-09 2002-03-12 Bops, Incorporated Methods and apparatus for instruction addressing in indirect VLIW processors
US6839728B2 (en) * 1998-10-09 2005-01-04 Pts Corporation Efficient complex multiplication and fast fourier transform (FFT) implementation on the manarray architecture
US6826522B1 (en) * 1999-06-21 2004-11-30 Pts Corporation Methods and apparatus for improved efficiency in pipeline simulation and emulation
US6748517B1 (en) * 1999-06-22 2004-06-08 Pts Corporation Constructing database representing manifold array architecture instruction set for use in support tool code creation
WO2001016702A1 (en) 1999-09-01 2001-03-08 Intel Corporation Register set used in multithreaded parallel processor architecture
JP3971535B2 (ja) * 1999-09-10 2007-09-05 株式会社リコー Simd型プロセッサ
JP3730455B2 (ja) * 1999-10-01 2006-01-05 富士通株式会社 情報処理装置及び情報処理方法
US20010049757A1 (en) * 2000-03-01 2001-12-06 Ming-Kang Liu Programmable task scheduler for use with multiport xDSL processing system
RU2158319C1 (ru) * 2000-04-25 2000-10-27 Институт металлургии и материаловедения им. А.А. Байкова РАН Высокопрочная коррозионно- и износостойкая аустенитная сталь
US7681018B2 (en) * 2000-08-31 2010-03-16 Intel Corporation Method and apparatus for providing large register address space while maximizing cycletime performance for a multi-threaded register file set
JP4502532B2 (ja) * 2001-02-23 2010-07-14 株式会社ルネサステクノロジ データ処理装置
AU2002367711A1 (en) 2001-06-14 2003-10-20 Hyperion Catalysis International, Inc. Field emission devices using modified carbon nanotubes
GB2382886B (en) * 2001-10-31 2006-03-15 Alphamosaic Ltd Vector processing system
US7398374B2 (en) * 2002-02-27 2008-07-08 Hewlett-Packard Development Company, L.P. Multi-cluster processor for processing instructions of one or more instruction threads
WO2003084243A1 (en) 2002-03-28 2003-10-09 Sony Corporation Image compression/encoding device, method, and program
JP3856737B2 (ja) * 2002-07-19 2006-12-13 株式会社ルネサステクノロジ データ処理装置
AU2003283777A1 (en) * 2002-12-30 2004-07-22 Koninklijke Philips Electronics N.V. Processing system
KR101132341B1 (ko) * 2003-04-07 2012-04-05 코닌클리즈케 필립스 일렉트로닉스 엔.브이. 데이터 처리 시스템 및 클러스터화된 명령 레벨 병렬성 프로세서
JP2007503039A (ja) * 2003-08-15 2007-02-15 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ 並列処理アレイ
US20050216700A1 (en) * 2004-03-26 2005-09-29 Hooman Honary Reconfigurable parallelism architecture
US7299339B2 (en) * 2004-08-30 2007-11-20 The Boeing Company Super-reconfigurable fabric architecture (SURFA): a multi-FPGA parallel processing architecture for COTS hybrid computing framework
US7890735B2 (en) * 2004-08-30 2011-02-15 Texas Instruments Incorporated Multi-threading processors, integrated circuit devices, systems, and processes of operation and manufacture
JP5240424B2 (ja) * 2004-11-05 2013-07-17 日本電気株式会社 Simd型並列演算装置、プロセッシング・エレメント、simd型並列演算装置の制御方式
US7493474B1 (en) * 2004-11-10 2009-02-17 Altera Corporation Methods and apparatus for transforming, loading, and executing super-set instructions
KR100636596B1 (ko) * 2004-11-25 2006-10-23 한국전자통신연구원 고에너지 효율 병렬 처리 데이터 패스 구조
US7912311B2 (en) * 2005-03-21 2011-03-22 Intel Corporation Techniques to filter media signals
KR101270925B1 (ko) * 2005-05-20 2013-06-07 소니 주식회사 신호 처리 장치
US8077174B2 (en) 2005-12-16 2011-12-13 Nvidia Corporation Hierarchical processor array
US7634637B1 (en) * 2005-12-16 2009-12-15 Nvidia Corporation Execution of parallel groups of threads with per-instruction serialization
US20080046684A1 (en) * 2006-08-17 2008-02-21 International Business Machines Corporation Multithreaded multicore uniprocessor and a heterogeneous multiprocessor incorporating the same
US8099583B2 (en) * 2006-08-23 2012-01-17 Axis Semiconductor, Inc. Method of and apparatus and architecture for real time signal processing by switch-controlled programmable processor configuring and flexible pipeline and parallel processing
US7797514B2 (en) * 2006-11-16 2010-09-14 Texas Instruments Incorporated Scalable multi-threaded sequencing/synchronizing processor architecture
US9354890B1 (en) 2007-10-23 2016-05-31 Marvell International Ltd. Call stack structure for enabling execution of code outside of a subroutine and between call stack frames
US8261025B2 (en) 2007-11-12 2012-09-04 International Business Machines Corporation Software pipelining on a network on chip
US8095775B1 (en) * 2007-11-21 2012-01-10 Marvell International Ltd. Instruction pointers in very long instruction words
US8526422B2 (en) 2007-11-27 2013-09-03 International Business Machines Corporation Network on chip with partitions
US7917703B2 (en) * 2007-12-13 2011-03-29 International Business Machines Corporation Network on chip that maintains cache coherency with invalidate commands
US8473667B2 (en) 2008-01-11 2013-06-25 International Business Machines Corporation Network on chip that maintains cache coherency with invalidation messages
US8010750B2 (en) * 2008-01-17 2011-08-30 International Business Machines Corporation Network on chip that maintains cache coherency with invalidate commands
US9442758B1 (en) 2008-01-21 2016-09-13 Marvell International Ltd. Dynamic processor core switching
US8018466B2 (en) * 2008-02-12 2011-09-13 International Business Machines Corporation Graphics rendering on a network on chip
US7913010B2 (en) * 2008-02-15 2011-03-22 International Business Machines Corporation Network on chip with a low latency, high bandwidth application messaging interconnect
US8490110B2 (en) 2008-02-15 2013-07-16 International Business Machines Corporation Network on chip with a low latency, high bandwidth application messaging interconnect
US8103853B2 (en) * 2008-03-05 2012-01-24 The Boeing Company Intelligent fabric system on a chip
US20090245257A1 (en) * 2008-04-01 2009-10-01 International Business Machines Corporation Network On Chip
US20090271172A1 (en) * 2008-04-24 2009-10-29 International Business Machines Corporation Emulating A Computer Run Time Environment
US8078850B2 (en) * 2008-04-24 2011-12-13 International Business Machines Corporation Branch prediction technique using instruction for resetting result table pointer
US8423715B2 (en) 2008-05-01 2013-04-16 International Business Machines Corporation Memory management among levels of cache in a memory hierarchy
KR100960148B1 (ko) * 2008-05-07 2010-05-27 한국전자통신연구원 데이터 프로세싱 회로
US7958340B2 (en) * 2008-05-09 2011-06-07 International Business Machines Corporation Monitoring software pipeline performance on a network on chip
US8494833B2 (en) 2008-05-09 2013-07-23 International Business Machines Corporation Emulating a computer run time environment
US8214845B2 (en) 2008-05-09 2012-07-03 International Business Machines Corporation Context switching in a network on chip by thread saving and restoring pointers to memory arrays containing valid message data
US8392664B2 (en) 2008-05-09 2013-03-05 International Business Machines Corporation Network on chip
US7861065B2 (en) * 2008-05-09 2010-12-28 International Business Machines Corporation Preferential dispatching of computer program instructions
US8020168B2 (en) * 2008-05-09 2011-09-13 International Business Machines Corporation Dynamic virtual software pipelining on a network on chip
US7991978B2 (en) * 2008-05-09 2011-08-02 International Business Machines Corporation Network on chip with low latency, high bandwidth application messaging interconnects that abstract hardware inter-thread data communications into an architected state of a processor
US8230179B2 (en) 2008-05-15 2012-07-24 International Business Machines Corporation Administering non-cacheable memory load instructions
US8040799B2 (en) * 2008-05-15 2011-10-18 International Business Machines Corporation Network on chip with minimum guaranteed bandwidth for virtual communications channels
US8078833B2 (en) * 2008-05-29 2011-12-13 Axis Semiconductor, Inc. Microprocessor with highly configurable pipeline and executional unit internal hierarchal structures, optimizable for different types of computational functions
US8181003B2 (en) * 2008-05-29 2012-05-15 Axis Semiconductor, Inc. Instruction set design, control and communication in programmable microprocessor cores and the like
US8438578B2 (en) 2008-06-09 2013-05-07 International Business Machines Corporation Network on chip with an I/O accelerator
JP2010039625A (ja) * 2008-08-01 2010-02-18 Renesas Technology Corp 並列演算装置
US8195884B2 (en) * 2008-09-18 2012-06-05 International Business Machines Corporation Network on chip with caching restrictions for pages of computer memory
WO2011094346A1 (en) * 2010-01-26 2011-08-04 Hobbs Barry L Integrated concurrent multi-standard encoder, decoder and transcoder
US9582443B1 (en) 2010-02-12 2017-02-28 Marvell International Ltd. Serial control channel processor for executing time-based instructions
GB2486485B (en) 2010-12-16 2012-12-19 Imagination Tech Ltd Method and apparatus for scheduling the issue of instructions in a microprocessor using multiple phases of execution
US8884920B1 (en) 2011-05-25 2014-11-11 Marvell International Ltd. Programmatic sensing of capacitive sensors
US9098694B1 (en) 2011-07-06 2015-08-04 Marvell International Ltd. Clone-resistant logic
US9069553B2 (en) 2011-09-06 2015-06-30 Marvell World Trade Ltd. Switching tasks between heterogeneous cores
US10565036B1 (en) 2019-02-14 2020-02-18 Axis Semiconductor, Inc. Method of synchronizing host and coprocessor operations via FIFO communication
CN112230995A (zh) * 2020-10-13 2021-01-15 广东省新一代通信与网络创新研究院 一种指令的生成方法、装置以及电子设备

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0740252B2 (ja) * 1986-03-08 1995-05-01 株式会社日立製作所 マルチプロセツサシステム
DE4129614C2 (de) * 1990-09-07 2002-03-21 Hitachi Ltd System und Verfahren zur Datenverarbeitung
US5963745A (en) * 1990-11-13 1999-10-05 International Business Machines Corporation APAP I/O programmable router
US5765011A (en) * 1990-11-13 1998-06-09 International Business Machines Corporation Parallel processing system having a synchronous SIMD processing with processing elements emulating SIMD operation using individual instruction streams
US6002880A (en) * 1992-12-29 1999-12-14 Philips Electronics North America Corporation VLIW processor with less instruction issue slots than functional units
US5682491A (en) * 1994-12-29 1997-10-28 International Business Machines Corporation Selective processing and routing of results among processors controlled by decoding instructions using mask value derived from instruction tag and processor identifier
US5649135A (en) * 1995-01-17 1997-07-15 International Business Machines Corporation Parallel processing system and method using surrogate instructions
US5680597A (en) * 1995-01-26 1997-10-21 International Business Machines Corporation System with flexible local control for modifying same instruction partially in different processor of a SIMD computer system to execute dissimilar sequences of instructions
US5659785A (en) * 1995-02-10 1997-08-19 International Business Machines Corporation Array processor communication architecture with broadcast processor instructions
US5669001A (en) * 1995-03-23 1997-09-16 International Business Machines Corporation Object code compatible representation of very long instruction word programs
US5870576A (en) * 1996-12-16 1999-02-09 Hewlett-Packard Company Method and apparatus for storing and expanding variable-length program instructions upon detection of a miss condition within an instruction cache containing pointers to compressed instructions for wide instruction word processor architectures
US6026478A (en) * 1997-08-01 2000-02-15 Micron Technology, Inc. Split embedded DRAM processor
US6076154A (en) * 1998-01-16 2000-06-13 U.S. Philips Corporation VLIW processor has different functional units operating on commands of different widths

Also Published As

Publication number Publication date
US6446191B1 (en) 2002-09-03
CA2310584A1 (en) 1999-05-20
US6151668A (en) 2000-11-21
IL135953A0 (en) 2001-05-20
EP1029266B1 (de) 2007-05-16
KR20010031884A (ko) 2001-04-16
CN1278342A (zh) 2000-12-27
JP2001523023A (ja) 2001-11-20
EP1029266A4 (de) 2005-08-17
DE69837791T2 (de) 2007-10-18
EP1029266A1 (de) 2000-08-23
JP4156794B2 (ja) 2008-09-24
WO1999024903A1 (en) 1999-05-20
CN100380313C (zh) 2008-04-09
USRE41703E1 (en) 2010-09-14
ATE362623T1 (de) 2007-06-15

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